RDC-50002: Reconvergence of Multiple Asynchronous Reset Synchronizers in a Common Reset Domain


Violations of this rule identify nodes that are reachable by different asynchronous reset synchronizer chains, where each chain synchronizes the same reset signal. Since asynchronous reset synchronizers may not come out of reset on the same clock cycle, the logic reaching the nodes violating this rule may contain both active and reset data at the same time.


Use the output of the same reset synchronizer chain for resetting all registers in a fan-out cone. If the reset signal is timing critical, add a pipelined reset tree after the reset synchronizer to close timing.

If the reset domain crossing is intended, then you can ignore or waive the rule.




Tag Description

Device Family

  • Intel® Cyclone® 10 GX
  • Intel® Arria® 10
  • Intel® Stratix® 10
  • Intel® Agilex™