LNT-30020: Same Signal Source Drives Synchronous and Asynchronous Ports of the Same Register


Violations of this rule identify registers that have a common signal source driving into both synchronous and asynchronous ports on the same register. This is usually a sign of unintended redundancy that can often be the source of bugs and which can be simplified while preserving the design intent.

Figure 1. Signal Race Problem Example.. The following image shows an example of the same signal source driving the synchronous port and the preset port of the same register:

For example, the following code creates a violation because it includes the same signal (sys_rst) in a register's asynchronous sensitity list and its synchronous logic:

always @(posedge clk, posedge sys_rst) begin   if(sys_rst)     rst_out <= 0;   else     rst_out <= sys_rst | sw_rst; // combine system reset with SW reset end


Remove any redundancy in the register's synchronous and asynchronous logic.




Tag Description
nonstandard-timing Design rule checks related to topologies which have unique timing analysis methodologies and may prove problematic.

Device Family

  • Intel Agilex®
  • Intel Agilex®
  • Intel®Cyclone® 10 GX
  • Intel®Stratix® 10
  • Intel®Arria® 10