RES-50004: Multiple Asynchronous Resets within Reset Synchronizer Chain


Violations of this rule identify asynchronous reset synchronizer chains where not all of the registers are reset by the same signal. Such chains do not properly synchronize the reset signal feeding the head of the chain. This condition can cause metastablity in downstream data signals.


Ensure that there is a common source that feeds the asynchronous reset pin of every register in the same asynchronous reset synchronizer chain.

Figure 1. Multiple Asynchronous Resets Driving Many Registers in a Reset Chain.. The following figures show multiple asynchronous resets within a reset chain that triggers Design Assistant violation RES-50004.
Figure 2. Sub-Optimal Asynchronous Resets Driving Many Registers in a Reset Chain




Tag Description
synchronizer Design rule checks related to synchronizer chains.

Device Family

  • Intel®Cyclone® 10 GX
  • Intel®Arria® 10
  • Intel®Stratix® 10
  • Intel Agilex®
  • Intel Agilex®
  • Intel Agilex®