CDC-50002: 1-Bit Asynchronous Transfer with Insufficient Constraints


Violations of this rule identify a synchronizer chain following a single-bit asynchronous data transfer with insufficient timing constraints. Such paths must be constrained in a way that prevents the Timing Analyzer from analyzing them as timed, synchronous transfers.

A data transfer is considered asynchronous if its launch and latch clocks are unrelated or asynchronous. Clocks are unrelated if they do not share a common parent clock. Clocks are asynchronous if they are explicitly designated as such via a clock group or clock-to-clock false path. Data transfers are also asynchronous if their destination register has the Synchronizer Identification = FORCED instance assignment.


Either apply the set_false_path or set_clock_groups -asynchronous constraint, or relax the timing on the transfer with a set_max_delay constraint with a value greater than the latch clock's period. Applying a max delay of any other value is not sufficient to satisfy this rule.

If a violating transfer was not intended to be asynchronous, ensure that the launch clock of the transfer is correct and is related to the latch clock of the transfer.

Figure 1. Synchronized 1-bit Asynchronous Transfer.. To prevent a CDC-50002 violation, there must be either a false path, asynchronous clock group, or relaxing max delay on the transfer from the orange register to the leftmost blue register in the following figure:




Tag Description

Device Family

  • Intel® Cyclone® 10 GX
  • Intel® Arria® 10
  • Intel® Stratix® 10
  • Intel® Agilex™