LNT-50007: Unregistered DSP Chain Connections
Description
DSPs are connected in an unregistered chain after synthesis. This will impede final Fmax and is not corrected by later register-packing optimizations.
Parameters
| Name | Description | Type | Default Value | Min Value | Max Value |
|---|---|---|---|---|---|
| DSP_High_Fanout_Net_Threshold | Fanout theshold for High Fanout Net (HFN) in DSP check | integer | 500 | 1 | |
| DSP_Chain_Threshold | Chain-length threshold for unregistered DSP chain connections | integer | 2 | 1 | |
| DSP_Check_User_WYSIWYGs | Check directly instantiated DSPs | bool | True |
Recommendation
For inferred DSPs, ensure that there are unprotected register stages on the output of the packed adders for synthesis to absorb during DSP inference. For directly instantiated DSPs, enable the output stage pipeline registers using parameter settings and connect an appropriate clock and/or reset if needed.
Severity
Medium
Tags
| Tag | Description |
|---|---|
| dsp | Design rule checks related to DSP blocks inside the FPGA fabric. |
| logic-levels | Design rule checks which flag potentially problematic amounts of logic on a timing path. |
| synthesis | Design rule checks which pertain to the Compiler's Analysis & Synthesis stage. |
Device Family
- Agilex®
- Agilex®
- Agilex®
- Stratix® 10