FLP-40006: Pipelining Registers That Might Be Recoverable
Description
Violations of this rule identify pipelined register buses that might be reduced in depth to save area with minimal impact to performance or retiming.
Parameters
| Name | Description | Type | Default Value | Min Value | Max Value |
|---|---|---|---|---|---|
| max_stage_adjustment | Reports a violation for buses that have a maximum recommended pipelining stage adjustment below and include the value of this parameter. | integer | -1 | ||
| min_width | Reports a violation for buses that have a minimum bus width above and include the value of this parameter. | integer | 16 | ||
| min_depth | Reports a violation for buses that have a minimum bus depth above and include the value of this parameter. | integer | 3 |
Recommendation
Reduce the depth of the violated pipelines.
Severity
Low
Tags
| Tag | Description |
|---|---|
| resource-usage | Design rule checks related to managing the resource usage of the design. |
Device Family
- Intel®Stratix® 10
- Intel Agilex®