FLP-40001: Congested Placement Region


High utilization, localized to a certain region, may lead to congestion and long routing detours having adverse impact on timing of critical nets in the region.

One or more of the following sub-optimal floorplanning decisions causes this condition:

  • Pin planning
  • Smaller Logic Lock region for the associated logic partition or partial reconfiguration (PR) partitions.
  • Incorrect placement of Logic Lock region.
  • Sub-optimal shape of Logic Lock region.


Name Description Type Default Value Min Value Max Value
region_placement_threshold (%) A violation is reported for placement regions that have placement congestion higher than specified in this parameter. double 70.0 100.0 0.0


Review whether the Logic Lock region is sufficiently large enough to contain the associated logic, or if it needs to be moved or reshaped to follow connectivity of the interface logic.




Tag Description
region-constraints Design rule checks related to region constraints in the design (both placement and routing).

Device Family

  • Intel Agilex®
  • Intel Agilex®
  • Intel Agilex®
  • Intel®Stratix® 10
  • Intel®Arria® 10
  • Intel®Cyclone® 10 GX