RES-50003: Asynchronous Reset with Insufficient Constraints


Violations of this rule identify asynchronous reset synchronizer chains where the reset signal feeding its registers has insufficient timing constraints. The release of the asynchronous signal feeding a reset synchronizer chain must be constrained in a way that prevents the Timing Analyzer from treating it as a timed, synchronous transfer.

Design Assistant can identify a reset transfer as asynchronous under any of the following conditions:

  • The reset signal is from an unconstrained input
  • The clock domain of the reset signal is unrelated/asynchronous to the latching domain of the register being reset


Constrain the reset signal feeding a reset chain with a set_false_path or set_clock_groups constraint, or relax the timing on the transfer with a set_max_delay constraint with a value greater than the latch clock's period. Applying a max delay of any other value is not sufficient to satisfy this rule.

Figure 1. Reset Synchronizer Chain Example.. The following figure shows a asynchronous reset synchronizer chain. To prevent Design Assistant violation RES-50003, specify a false path, asynchronous clock group, or relaxing maximum delay on the transfers from the async reset source to all of the registers' async reset pins.




Tag Description
synchronizer Design rule checks related to synchronizer chains.

Device Family

  • Intel®Cyclone® 10 GX
  • Intel®Arria® 10
  • Intel®Stratix® 10
  • Intel Agilex®
  • Intel Agilex®
  • Intel Agilex®