CDC-50006: CDC Bus Constructed with Unsynchronized Registers

Description

Violations of this rule identify multi-bit unsynchronized transfers that form a CDC bus.

Figure 1. An unsynchronized CDC bus transfer.. The following figure shows a CDC bus transfer. To prevent a CDC-50006 violation, each destination register must be followed by the same number of registers also latched by clkB .

Recommendation

If the bus does not transfer gray-coded data, replace the existing CDC handshake circuit with the Bus Synchronizer Parameterizable Macro (ipm_cdc_bus_sync).

Refer to the documentation of Insert Template Dialog Box for instructions on adding (or instantiating) this macro.

To resolve the violation without replacing the circuit with the Bus Synchronizer Parameterizable Macro, change its implementation to incorporate a control signal, since synchronizer chains are not sufficient to ensure that all bits of the bus latch on the same clock cycle.

If the bus transfers gray-coded data, protect it using synchronizer chains. To do this, ensure that the destination of each bit forms a chain of two or more registers, with each register in the same clock domain as the destination of the bus transfer, and with no combinational logic between any of the registers in any of the chains. Also, ensure that there is no combinational logic on the bus transfer, and that the chains following each bit all contain the same number of registers.

Figure 2. A balanced CDC bus.

Severity

High

Tags

Tag Description
synchronizer Design rule checks related to synchronizer chains.
cdc-bus Design rule checks related to topologies that use a bus to transfer multiple bits of data between clock domains at once.

Device Family

  • Intel®Cyclone® 10 GX
  • Intel®Arria® 10
  • Intel®Stratix® 10
  • Intel Agilex®
  • Intel Agilex®
  • Intel Agilex®