RES-50101: Intra-Clock False Path Reset Synchronizer


Violations of this rule identify a reset synchronizer that was identified from the destination of an intra-clock false path. To preserve the original behaviour of IP, the Intel Quartus Prime software conservatively treats such transfers as asynchronous, despite being between the same clock.


If an intra-clock false path is required and does not need to be followed by a reset synchronizer, use set_false_path to cut the path, instead of set_false_path .




Tag Description
synchronizer Design rule checks related to synchronizer chains.
false-positive-synchronizer Design rule checks related to automatically-deteected synchronizer chains that may have been over-zealously detected.

Device Family

  • Intel®Cyclone® 10 GX
  • Intel®Arria® 10
  • Intel®Stratix® 10
  • Intel Agilex®
  • Intel Agilex®
  • Intel Agilex®