FLP-10501: Top-Level Ports Without Pin Location Assignment

Description

Violations of this rule idenfity top-level ports that do not have designated physical location assignments. Unconstrained pins can be relocated depending on changes to the design and seed; setting these location constraints ensures that I/O locations will not change. I/O Location differences can also change the HPS IO hash and block you from configure the FPGA fabric in HPS Boot First mode.

Recommendation

Add Location QSF Assignments for unassigned top-level ports.

set_location_assignment PIN_<ID> -to <pin_name>

Severity

Medium

Tags

Tag Description
system Design rule checks which validate full-system design.

Device Family

  • Stratix® 10
  • Agilex®
  • Agilex®
  • Agilex®
  • Arria® 10
  • Cyclone® 10 GX