LNT-30017: Register Output Driving Its Own Asynchronous Control Signal Directly or Through Combinational Logic


Violations of this rule identify registers with asynchronous control signals that are driven by the register's output, either directly or through combinational logic.

Figure 1. Example register driving its own asynchronous control signal directly
Figure 2. Example register driving its own asynchronous control signal through combinational logic

Structures such as these can cause instability and unreliability in the circuit, because the output of each violating register is a signal race back to itself with no guarantee that it will stabilize before each clock edge.

The register and any downstream combinational logic feeding its asynchronous port can be visualized by right-clicking the violation and selecting "Locate Node->Locate in RTL Viewer".


Restructure the netlist to break the dependency of the register's asynchronous control signal on its output, either by cutting edges or by inserting register stages.




Tag Description
nonstandard-timing Design rule checks related to topologies which have unique timing analysis methodologies and may prove problematic.

Device Family

  • Intel Agilex®
  • Intel Agilex®
  • Intel Agilex®
  • Intel®Stratix® 10
  • Intel®Arria® 10
  • Intel®Cyclone® 10 GX