CDC-50101: Intra-Clock False Path Synchronizer

Description

Violations of this rule identify a synchronizer chain that follows an intra-clock false path. To preserve the original behaviour of IP, the Intel Quartus Prime software conservatively treats intra-clock false paths as asynchronous, despite them not involving a clock crossing at all.

Figure 1. An intra-clock false path followed by a deduced synchronizer chain.

Recommendation

If an intra-clock false path is required and is not meant to be asynchronous, use set_false_path to cut the path, instead of set_false_path . If a set_false_path is intended for an intra-clock false path, waive the violation.

Severity

Low

Tags

Tag Description
synchronizer Design rule checks related to synchronizer chains.
false-positive-synchronizer Design rule checks related to automatically-deteected synchronizer chains that may have been over-zealously detected.

Device Family

  • Cyclone® 10 GX
  • Arria® 10
  • Stratix® 10
  • Agilex®
  • Agilex®
  • Agilex®