LNT-30022: Same Signal Source Drives Clock Port and Another Port of a Register
Description
Violations of this rule identify registers that have a common signal source driving into both their clock port and any other port on the same register. This is commonly unintentional and can result in timing instability if not carefully implemented and constrained.
Recommendation
Ensure that the violating registers have independent synchronous sources between their clock and non-clock ports.
Severity
Low
Tags
Tag | Description |
---|---|
nonstandard-timing | Design rule checks related to topologies which have unique timing analysis methodologies and may prove problematic. |
Device Family
- Intel Agilex®
- Intel Agilex®
- Intel Agilex®
- Intel®Cyclone® 10 GX
- Intel®Stratix® 10
- Intel®Arria® 10