LNT-30011: Design Contains Combinational Loops


Violations of this rule identify combinational loops detected in the synthesized netlist. A combinational loop is combinational logic that drives itself without synchronization by a register.

Figure 1. Combinational Loop

Combinational loops can result in instability and unreliability in the circuit. For example, due to the following reasons, the combinational loop after fitting may not function as originally intended in the design:

  • The behavior of a combinational loop often depends on the relative propagation delays of the combinational loop's logic.
  • Design tools experience difficulties when handling combinational loops.

The full structure detected in each violation contains one or more intersecting combinational loops. The entire structure can be visualized by right-clicking the violation and selecting "Locate Node->Locate in RTL Viewer".


Restructure the netlist to break all combinational loops within each violating structure by cutting feedback edges and/or by inserting register stages.




Tag Description
nonstandard-timing Design rule checks related to topologies which have unique timing analysis methodologies and may prove problematic.

Device Family

  • Intel Agilex®
  • Intel®Stratix® 10
  • Intel®Arria® 10
  • Intel®Cyclone® 10 GX