TMC-20206: DSP Blocks with Unregistered Outputs that are the Source of Paths Failing Setup Analysis
Description
Violations of this rule identify DSP blocks with unregistered outputs that are sources of paths that fail setup analysis. Registering DSP outputs can significantly improve DSP's μtco/cell delay.
Parameters
| Name | Description | Type | Default Value | Min Value | Max Value |
|---|---|---|---|---|---|
| maximum_setup_slack | Reports a violation for timing paths that have a setup slack below the value of this parameter. | double | 0.0 | ||
| to_clock_filter | Reports a violation for timing paths that end at a register in a clock domain that matches the value of this parameter. | string | * | ||
| minimum_number_of_adders | Reports a violation for timing endpoints that are preceded by a number of independent adder chains greater than or equal to this value. | integer | 3 | ||
| minimum_number_of_soft_mult_chains | Reports a violation for timing endpoints that are preceded by a number of independent adder chains that are implementing multiplier logic greater than or equal to this value. | integer | 2 |
Recommendation
Add pipeline(s) to the DSP's output path to register DSP's output. Also make sure DSP packing rules are not violated to allow successful register-packing. Review the Fitter reports 'Fixed Point DSP Register Packing Details' and 'Floating Point DSP Block Details' for more details.
Severity
Medium
Tags
| Tag | Description |
|---|---|
| dsp | Design rule checks related to DSP blocks inside the FPGA fabric. |
Device Family
- Intel®Stratix® 10
- Intel Agilex®
- Intel Agilex®
- Intel®Arria® 10
- Intel®Cyclone® 10 GX