TMC-20010: Logic Level Depth


Large logic level depth restricts the clock speed at which the circuit can operate.

Note: Specify the Logic_Level_Threshold parameter to modify the threshold value for deep logic level depth paths.


Name Description Type Default Value Min Value Max Value
logic_level_threshold Reports a violation for paths that have logic levels more than specified in this parameter. integer 5   1
to_clock Only reports a violation for paths associated to the clock domains that match this filter. string *    


Restructure the design by adding pipeline registers to remove performance bottlenecks and increase achievable clock frequency for the design.




Tag Description
logic-levels Design rule checks which flag potentially problematic amounts of logic on a timing path.

Device Family

  • Intel Agilex®
  • Intel Agilex®
  • Intel Agilex®
  • Intel®Stratix® 10
  • Intel®Arria® 10
  • Intel®Cyclone® 10 GX