Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 11/01/2022

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Document Table of Contents

6.1. Top-Level Settings

Figure 27. Multi Channel DMA IP for PCI Express Parameter Editor
Table 68.  Top-Level Settings



Default Value


Hard IP mode

Gen4 x16, Interface – 512 bit

Gen3 x16, Interface – 512 bit

Gen4 2x8, Interface - 256 bit

Gen3 2x8, Interface - 256 bit

Gen4 1x8, Interface – 256 bit

Gen3 1x8, Interface – 256 bit

Gen4x16, Interface – 512 bit

Select the following elements:
  • Lane data rate: Gen3 and Gen4 are supported.
  • Lane width: x16 and x8 modes support both Root Port and Endpoint.
Number of PCIe 1 / 2 1

Display total number of MCDMA IP cores in x8 mode.

Port Mode

Native Endpoint

Root Port

Native Endpoint

Specifies the port type.

Root Port mode: x16,1x8 (F-Tile only)

Endpoint mode: x16, 1x8, 2x8

Enable Ptile Debug Toolkit (P-Tile)

Enable Debug Toolkit (F-Tile)

On / Off


Enable the Debug Toolkit for JTAG-based System Console debug access.

Enable PHY Reconfiguration

On / Off


When on, creates an Avalon-MM slave interface that software can drive to update Transceiver reconfiguration registers

Enable the transceiver PMA registers access through a dedicated an Avalon-MM slave interface.

Note: In F-Tile, this option has renamed as Enable PMA registers access

PLD Clock Frequency

500 MHz

450 MHz

400 MHz

350 MHz

250 MHz

225 MHz

200 MHz

175 MHz

350 MHz (for Gen4 modes)

250 MHz (for Gen3 modes)

Select the frequency of the Application clock. The options available vary depending on the setting of the Hard IP Mode parameter.

For Gen4 modes, the available clock frequencies are 500 MHz / 450 MHz / 400 MHz / 350 MHz / 250 MHz / 225 MHz / 200 MHz / 175 MHz (for Intel Agilex) and 400 MHz / 350 MHz / 200 MHz /175 MHz (for Intel Stratix 10 DX).

For Gen3 modes, the available clock frequency is 250 MHz (for Intel Agilex and Intel Stratix 10 DX).

Enable SRIS Mode

On / Off


Enable the Separate Reference Clock with Independent Spread Spectrum Clocking (SRIS) feature.

When you enable this option, the Slot clock configuration option under the PCIe Settings → PCIe PCI Express/PCI Capabilities → PCIe Link tab will be automatically disabled.

P-Tile Sim Mode

On / Off


Enabling this parameter reduces the simulation time of Hot Reset tests by 5 ms.

Note: Do not enable this option if you need to run synthesis.
Note: This option is not available for F-Tile.
Enable Independent Perst On / Off Off

Enable the reset of PCS and Controller in User Mode for Endpoint 2x8 mode.

When this parameter is On, new signals , p<n>_pld_clrpcs_n, are exported to user application.

When this parameter is Off (default), the IP internally ties off these signals instead of exporting them.

Note: This parameter is required for the independent reset feature, which is only supported in the x8x8 Endpoint/Endpoint mode.
Note: For more information regarding the independent resets feature and its usage, refer to P-Tile Avalon Streaming Intel FPGA IP for PCI Express User Guide Appendix E.
Enable CVP (Intel VSEC) On / Off Off

Enable support for CVP flow for single tile only

Refer to Intel Agilex Device Configuration via Protocol (CvP) Implementation User Guide for more information