Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 11/01/2022
Public
Document Table of Contents

1.2. Known Issues

The following summarizes known issues in the current IP release:
  1. MCDMA AVMM PIO may drop Posted Writes when user logic backpressures by asserting rx_pio_waitrequest_i
  2. In Intel® Agilex™ Gen4 x16 AVST 1 port mode, MCDMA Packet Generate/Check example design in Intel® Quartus® Prime 22.3 may violate setup time requirement at 500 MHz PLD clock frequency.
  3. When software resets a queue by writing 1 to Q_RESET register, other channels stop receiving traffic. You should ensure the system is quiescent before resetting a H2D queue.
  4. Multichannel D2H AVST configuration has stability issues when total number of D2H channels configured is greater than 256
Note: These issues will be addressed in a future release of Intel® Quartus® Prime.

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