Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 11/01/2022
Public
Document Table of Contents

2.1.1. Endpoint Mode

  • MCDMA P-Tile: PCIe Gen4/Gen3 x16/x8 in Intel® Stratix® 10 DX and Intel® Agilex™ devices.
  • MCDMA H-Tile: PCIe Gen3 x16/x8 in Intel® Stratix® 10 GX and Intel® Stratix® 10 MX devices.
  • MCDMA F-Tile: PCIe Gen4/Gen3 x16/x8 in Intel Agilex device
  • MCDMA P/F-Tiles: Gen4/Gen3 2x8 port bifurcation in Intel® Stratix® 10 DX and Intel® Agilex™ devices
  • User Mode options:
    • Multi Channel DMA
    • Bursting Avalon Master (BAM)
    • Bursting Avalon Slave (BAS)
    • BAM and BAS
    • BAM and MCDMA
    • Data Mover Only (available in MCDMA P-Tile and F-Tile IP's)
  • Supports up to 2K DMA channels.
    • Table 2.  Maximum DMA channels
      Device MCDMA Interface Type
      AVMM AVST

      Intel® Stratix® 10 GX

      Intel® Stratix® 10 MX

      Intel® Stratix® 10 DX

      Intel® Agilex™

      2048* 2048*
      Note: * = Maximum 512 channels per Function
  • Per Descriptor completion notification with MSI-X or Writebacks
  • Option to select Avalon-MM or Avalon-ST DMA for user logic interface
  • SR-IOV
  • User MSI-X in MCDMA mode
  • User FLR in MCDMA mode
  • MSI Interrupt in BAS
  • H2D address and payload size alignment to byte granularity for AVST
  • Maximum payload size supported:
    • Intel® Stratix® 10 GX and Intel® Stratix® 10 MX devices: 512 bytes
    • Intel® Stratix® 10 DX and Intel® Agilex™ devices: 512 / 256 / 128 bytes

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