Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 11/01/2022
Public
Document Table of Contents

1.1. Terms and Acronyms

Table 1.  Acronyms
Term Definition
API Application Programming Interface
ATT Address Translation Table
Avalon® -ST (or AVST) Avalon® Streaming Interface
Avalon® -MM (or AVMM) Avalon® Memory-Mapped Interface
BAS Bursting Avalon-MM Slave
BAM Bursting Avalon-MM Master
CvP Configuration via Protocol
D2H Device-to-Host
D2HDM Device-to-Host Data Mover
DMA Direct Memory Access
DPDK Data Path Development Kit
EOF End of a File (or packet) for streaming
EP End Point
FAE Field Applications Engineer
FLR Functional Level Reset
File (or Packet) A group of descriptors defined by SOF and EOF bits of the descriptor for the streaming. At Avalon-ST user interface, a file (or packet) is marked by means of sof/eof.
GCSR General Control and Status Register
H2DDM Host-to-Device Data Mover
H2D Host-to-Device
HIP Hard IP
HIDX Queue Head Index (pointer)
IMMWR Immediate Write Operation
IP Intellectual Property
MCDMA Multi Channel Direct Memory Access
MRRS Maximum Read Request Size
MSI-X Message Signaled Interrupt - Extended
MSI Message Signaled Interrupt
PBA Pending Bit Array
PD Packet Descriptor
PCIe* Peripheral Component Interconnect Express ( PCI Express* )
PIO Programmed Input/Output
PMD Poll Mode Driver
QCSR Queue Control and Status register
QID Queue Identification
RP Root Port
SOF Start of a File (or packet) for streaming
SR-IOV Single Root I/O Virtualization
TLP Transaction Layer Packet
TIDX Queue Tail Index (pointer)

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