Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 11/01/2022
Public
Document Table of Contents

3.1.3.1. Support for Unaligned (or byte-aligned) Data Transfer

MCDMA IP supports the following alignment modes for the descriptor source/destination address and payload count fields.

Table 17.  Alignment Mode
Alignment Mode IP GUI Parameter Setting SRC/DEST Address Alignment Payload Count Alignment Note
Default alignment Enable address byte aligned = FALSE

AVMM: DWORD aligned

AVST: 64-byte aligned (or full data width aligned)

AVMM: DWORD aligned

AVST: 64-byte aligned (exception: last descriptor of a packet/file)

  • Descriptors are 32-byte aligned
  • Low resource utilization
Unaligned (or Byte aligned) Access Enable address byte aligned = TRUE Byte aligned Byte aligned
  • Supported for H2D AVST Interface only
  • Descriptors are 32-byte aligned
  • DMA read requests use the PCIe First DWORD Byte Enable and Last DWORD Byte Enable to support byte granularity
  • High resource utilization

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