Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 11/01/2022
Public
Document Table of Contents

3.10.1.1. H2D Descriptor Format (h2ddm_desc)

Table 27.  H2D Descriptor Format
Name Width Description
SRC_ADDR [63:0] 64

Starting system address of allocated transmit buffer read by DMA.

DEST_ADDR [127:64] 64

Starting local AVMM address written by DMA.

PYLD_CNT [147:128] 20

Payload size in bytes.

MM_mode=0: The DMRd is meant for descriptor fetch and completion is returned on the Descriptor completion interface. In this case, upper 10 bits are reserved.

MM_Mode=1: The DMRd is for data fetch and completion is sent to AVMM Write master interface. In this case, entire 20 bits are valid. 20’h0 means 1MB.

RSVD 1 Reserved
App_specific_bits [151:149] 3

Application-specific bits. Reserved for H2D (0x0).

DESC_IDX1 [167:152] 16

Unique Identifier for each descriptor. The same ID is applied to the AVST source status signaling interface (h2ddm_desc_status) returning the status of the Data mover completion to DMA controller.

RSVD [173:168] 6

Reserved

MCDMA mode [174:174] 1

Hardwired to 0.

Indicates Data Mover mode, i.e., external DMA.

MM_mode [175:175] 1

MM_mode=0: Indication to H2D Data Mover to transfer the completion to AVST source CMPL interface (h2dm_desc_cmpl) to external DMA controller. Descriptor fetches happen only on the H2D Data Mover with MM_mode=0.

MM_mode=1: Indication to H2D Data Mover to transfer the data to AVMM interface. Indicates that the descriptor is a data movement command. DMRd command with MM_mode=1 reads the data from host memory and write it to local FPGA memory.

DM_FmtType [183:176] 8

‘h20=DMRd

PFVF [199:184] 16

{VF_ACTIVE, VFNUM[10:0], PF[3:0]}

RSVD [200:200] 1

Reserved

RSVD [216:201] 16

Reserved

DESC_IDX2 [228:217] 12

Optional.

Descriptor ID field providing additional provision for descriptor fetch engine to embed information such as channel number, etc. which the completion status on AVST will return unedited for the response completion packet.

If not used, the user external DMA controller is expected to drive this field to zero. The data mover subsystem will treat the descriptor ID field as {DESC_IDX2, DESC_IDX1}.

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