Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 11/01/2022
Public
Document Table of Contents

2. Introduction

Figure 1. Multi Channel DMA IP for PCI Express Usage in Server Hardware Infrastructure

The Multi Channel DMA IP for PCI Express enables you to efficiently transfer data between the host and device. The Multi Channel DMA IP for PCI Express supports multiple DMA channels between the host and device over the underlying PCIe link. A DMA channel consists of H2D (host to device) and D2H (device to host) queue pair.

As shown in the figure above, the Multi Channel DMA IP for PCI Express can be used in a server’s hardware infrastructure to allow communication between various VM-clients and their FPGA-device based counterparts. The Multi Channel DMA IP for PCI Express operates on descriptor-based queues set up by driver software to transfer data between local FPGA and host. The Multi Channel DMA IP for PCI Express’s control logic reads the queue descriptors and executes them.

The Multi Channel DMA IP for PCI Express integrates the Intel® PCIe* Hard IP and interfaces with the host Root Complex via the PCIe serial lanes. On the user logic interface, Avalon-MM/Avalon-ST interfaces allow the designer easy integration of the Multi Channel DMA IP for PCI Express with other Platform Designer components.

Besides DMA functionality, Multi Channel DMA IP for PCI Express enables standalone Endpoint or Rootport functionality with Avalon-MM interfaces to the user logic. This functionality is described in more detail in the Functional Description chapter.

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