Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 11/01/2022
Public
Document Table of Contents

3.3. Bursting Avalon-MM Slave (BAS)

The Avalon-MM TX Bursting slave module translates Avalon-MM Read and Write transactions from user logic to PCI Express Mrd and Mwr TLPs. The returned PCI Express CplD packets is translated to Avalon-MM interface as response to Avalon-MM read transaction.

The BAS supports both 256 bit and 512 bit data widths to achieve bandwidths required for Gen4 x8 and Gen4 x16. It supports bursts up to 512 bytes and multiple outstanding read requests. The default support is only for the 64 NP outstanding.

Figure 8. Bursting Avalon-MM Slave Definition

Completion Re-ordering

Avalon-MM BAS interface is slave interface to the User Avalon-MM. The User AVMM can initiate AVMM reads to host interface and this translates to BAS Non-Posted packet interface signals. The BAS module keeps track of the initiated NP requests and tracks against the completions received from the PCIe on the scheduler completion packet interface.

Since the completion from the PCIe can come out of order, the completion re-ordering module ensures the returned completions are re-ordered against the pending requests and send in the order on the AVMM interface since AVMM doesn’t track out of order completions.

Note: BAS AVMM Slave waitrequestAllowance is 0, which means BAS can accept 0 additional command cycle after waitrequest is asserted.

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