Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 11/01/2022
Public
Document Table of Contents

8.1.3. Application

At the time of starting the application, by using the APIs provided by driver, it reads the MCDMA capabilities, creates application context, open BAR registers, initializes the PCI Express functions. At the time of termination, it clears the application context and stops all the channels.

Multi-threading with Multiple Channels

Based on the input parameters, the application starts multiple threads with posix thread APIs, associate the queue to the thread and submit DMA transactions one at a time independently. As part of this, driver updates the tail register of that channel. Update tid ID update, hardware picks up the channel and start DMA operation.

Each thread performs the following tasks.
  1. Get the device context based on BDF (Bus Device Function)
  2. Acquire the available channel
  3. Get DMA capable memory
  4. Start DMA operation
  5. Release the channel

As multiple threads can try to grab and release the channel at a time, userspace driver (libmqdma) handles synchronization problems while performing channel management.

Scheduling Threads

As POSIX libraries are being used for thread management, Linux scheduler takes care of scheduling the threads, there is no custom scheduler which takes care of scheduling the threads.

perfq_app schedules multiple queues on single threads for DMA operations.
  1. Reads number of channels from user (-c <num>)
  2. Reads number of threads from user (-a <num>)
  3. Calculate number of queues DMA need to perform from one thread
  4. After every TID update, perfq_app swaps out a queue and swaps in other queue to perform DMA operation.

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