Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 11/01/2022
Public
Document Table of Contents

6.3.1. PCIe1 Configuration, Debug and Extension Options

Figure 33. PCIe1 Configuration, Debug and Extension Options
Table 87.  PCIe1 Configuration, Debug and Extension Options Settings Table
Parameter Value Default Value Description

Port 1 REFCLK init active

On / Off

On

If this parameter is On (default), the refclk1 is stable after pin_perst and is free-running. This parameter must be set to On for Type A/B/C systems.

If this parameter is Off, refclk1 is only available later in User Mode. This parameter must be set to Off for Type D systems.

This parameter is only available in the PCIe1 Settings tab for a 2x8 topology.

For more details regarding the bifurcation feature and its usage, refer to P-Tile Avalon Streaming Intel FPGA IP for PCI Express User Guide Appendix E.

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