Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 11/01/2022
Public
Document Table of Contents

3.1.8. User Functional Level Reset (FLR)

When DMA engine receives Functional Level Resets from the PCIe Hard IP module, the reset requests are propagated to the downstream logic via this interface. In addition to performing resets to its internal logic, it waits for an acknowledgment from user logic for the reset request before it issues an acknowledgement to the PCIe Hard IP.

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