Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 11/01/2022
Public
Document Table of Contents

4.8. Config Slave Interface (RP only)

Table 46.  Config Slave Interface Signals
Signal Name I/O Type Description
cs_address_i[13:0] Input Represents a byte address. The value of address must align to the data width.
cs_byteenable_i[3:0] Input Enables one or more specific byte lanes during transfers on interfaces
cs_read_i Input Asserted to indicate a read transfer.
cs_readdata_o[31:0] Output Read data to the user logic in response to a read transfer
cs_readdatavalid_o Output When asserted, indicates that the readdata signal contains valid data.
cs_write_i Input Asserted to indicate a write transfer
cs_writedata_i[31:0] Input Data for write transfers
cs_writeresponse_valid_o Output Write responses for write commands. When asserted, the value on the response signal is a valid write response.
cs_waitrequest_o Output When asserted, indicates that the Avalon-MM slave is not ready to respond to a request.
cs_response_o[1:0] Output Carries the response status: 00: OKAY—Successful response for a transaction. 01: RESERVED—Encoding is reserved. 10: SLAVEERROR—Error from an endpoint agent. Indicates an unsuccessful transaction. 11: DECODEERROR—Indicates attempted access to an undefined location.

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