Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 4/20/2022
Public

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Document Table of Contents

4.4.7. User FLR Interface

Table 40.  User FLR Interface

Interface Clock Domain for H-Tile: coreclkout_hip

Interface Clock Domain for P-Tile and F-Tile: app_clk

Signal Name I/O Description
usr_flr_rcvd_val_o

Output

Indicates user logic to begin flr for the specifid channel in usr_flr_rcvd_chan_num_o. asserted until usr_flr_completed_i input is sampled 1’b1.

usr_flr_rcvd_chan_num_o[10:0]

Output

Indicates Channel number for which flr has to be initiated by user logic.

usr_flr_completed_i

Input

One-cycle pulse from the application indicates completion of flr activity for channel in usr_flr_rcvd_chan_num_o

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