Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 4/20/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.1.4. Multifunction and SR-IOV System Settings Parameters [Endpoint Mode]

Figure 18. Multifunction and SR-IOV System Settings Parameters
Table 58.  PCIe0 Multifunction and SR-IOV System settings
Parameter Value Description
Total physical functions (PFs) 1-4

Sets the number of physical functions

Enable SR-IOV support On / Off

Enable SR-IOV support

Total virtual functions of physical function (PF VFs) 0 (default)

Set the number of VFs to be assigned to each Physical Function

Enable SRIOV for PF0 On / Off

Enable SR-IOV support on Physical Function

Number of DMA channels allocated to PF0 0 - 512

Number of DMA Channels between the host and device PF Avalon-ST / Avalon-MM ports.

For 4 Port Avalon-ST interface type, only 1 channel per port is supported.

For 1 Port Avalon-ST interface type, up to 256 channels are supported.

For Avalon-MM Interface type, up to 2K channels (max 512 channels / function) are supported.

Number of DMA channels allocated to each VF in PF0 0 - 512

When SRIOV support is turned on for the PF, this parameter sets the number of DMA channels allocated to each VF in the PF

Note: This parameter is active when 'Enable SR-IOV support' is set to ON and 'Enable SRIOV for PF' is also set to ON.

Did you find the information on this page useful?

Characters remaining:

Feedback Message