Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 4/20/2022

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Document Table of Contents

10.1.1. Overview

The P-Tile Debug Toolkit is a System Console-based tool for P-Tile that provides real-time control, monitoring and debugging of the PCIe links at the Physical Layer.

The P-Tile Debug Toolkit allows you to:
  • View protocol and link status of the PCIe links.
  • View PLL and per-channel status of the PCIe links.
  • View the channel analog settings.
  • View the receiver eye and measure the eye height and width for each channel.
  • Indicate the presence of a re-timer connected between the link partners.
Note: The current version of Intel® Quartus® Prime supports enabling the Debug Toolkit for the Endpoint mode only, and with the Linux and Windows operating systems only.
Note: Debug Toolkit is not enabled in the Intel® Quartus® Prime 22.1 version for F-Tile. It may be available in future release.

The following figure provides an overview of the P-Tile Debug Toolkit in the P-Tile Multi Channel DMA IP for PCI Express.

Figure 54. Overview of the P-Tile Debug Toolkit

When you enable the P-Tile Debug Toolkit, the intel_pcie_ptile_mcdma module of the generated IP includes the Debug Toolkit modules and related logic as shown in the figure above.

Drive the Debug Toolkit from a System Console. The System Console connects to the Debug Toolkit via an Native PHY Debug Master Endpoint (NPDME). Make this connection via an Intel FPGA Download Cable.

The PHY reconfiguration interface clock (xcvr_reconfig_clk) is used to clock the following interfaces:
  • The NPDME module
  • PHY reconfiguration interface (xcvr_reconfig)
  • Hard IP reconfiguration interface (hip_reconfig)

Provide a clock source (50 MHz - 125 MHz, 100 MHz recommended clock frequency) to drive the xcvr_reconfig_clk clock. Use the output of the Reset Release Intel FPGA IP to drive the ninit_done, which provides the reset signal to the NPDME module.

Note: When you enable the P-Tile Debug Toolkit, the Hard IP Reconfiguration interface is enabled by default.
When you run a dynamically-generated design example on the Intel Development Kit, make sure that clock and reset signals are connected to their respective sources and appropriate pin assignments are made. Here is a sample .qsf assignments for the Debug Toolkit:
  • set_location_assignment PIN_C23 -to xcvr_reconfig_clk_clk