A DMA channel to support Multi Channel DMA data movement consists of a pair of the descriptor queues: one H2D descriptor queue and one D2H descriptor queue. Descriptors are arranged contiguously within a 4 KB page.
Each descriptor is 32 bytes in size. The descriptors are kept in host memory in a linked-list of 4 KB pages. For a 32 byte descriptor and a 4 KB page, each page contains upto 128 descriptors. The last descriptor in a 4 KB page must be a “link descriptor” – a descriptor containing a link to the next 4 KB page with the link bit set to 1. The last entry in the linked list must be a link pointing to the base address programmed in the QCSR, in order to achieve a circular buffer containing a linked-list of 4 KB pages. The figure below shows the descriptor linked list.
Software and hardware communicate and manage the descriptors using tail index pointer (Q_TAIL_POINTER) and head index pointer (Q_HEAD_POINTER) QCSR registers as shown in the following figure. The DMA starts when software writes the last valid descriptor index to the Q_TAIL_POINTER register.
If Link bit =0, then this field contains the source address.
Starting system address of allocated transmit buffer read by DMA that should be 64 byte aligned.
If the queue is H2D, then this field contains the address in Host Memory. If the queue is D2H, then this is the AVMM address in device memory.
If the link bit is set, then this contains the address of the next 4 KB page in host memory containing the descriptors.
Provided link=0, this field means:
Starting system address of allocated receive buffer written by DMA that should be 64 byte aligned.
If the queue is D2H, then this field contains the address in Host Memory. If the queue is H2D, then this is the AVMM address in device memory.
Provided link=0, this field means DMA payload size in bytes. Max 1 MB, with 20’h0 indicating 1 MB.
For a D2H queue in 1 port AVST mode, this field is a fixed value across all descriptors of the queue and must reflect the value in Q_PYLD_CNT (0x44) QCSR register.
Unique Identifier for each descriptor, assigned by the software driver. This value is written to Q_COMPLETED_POINTER register when a descriptor data transfer is complete.
Note: First descriptor DESC_IDX value is 1, not 0.
|MSIX_EN ||1||Enable MSI-X per descriptor|
|WB_EN ||1||Enable Write Back per descriptor|
|RX_PYLD_CNT [211:192]||20||Received actual payload for D2H data movement (upstream)|
SOF indicator for Avalon-ST streaming.
In the H2D streaming, this bit causes the Avalon-ST Source interface to assert h2d_st_sof_o, indicating start of a file/packet.
In the D2H streaming, this bit is set in the Descriptor itself, by MWr TLP when the user logic asserts d2h_st_sof_i, indicating start of a file/packet.
Note: In the H2D streaming, both SOF and EOF can be set in the same descriptor (file size = payload count) or it can span multiple descriptor pages.
Note: In the D2H streaming, if user logic prematurely ends the data transfer by asserting d2h_st_eof_i in the middle of a descriptor data move then starts a next file/packet, the SOF bit in the next descriptor is set by MWr TLP.
Note: SOF bit is an optional feature for DMAs involving file data transfers using Avalon-ST interface.
EOF indicator for Avalon-ST streaming.
In the H2D streaming, this bit causes the Avalon-ST Source interface to assert h2d_st_eof_o, indicating end of a file/packet.
In the D2H streaming, this bit is set within the descriptor itself by a Writeback (if Writeback is enabled) when the user logic asserts d2h_st_eof_i, indicating end of a packet.
Along with the EOF bit, MWr TLP also updates the actual received payload count (RX_PYLD_CNT) field of the last descriptor.
Note: EOF bit is an optional feature for DMAs involving file data transfers using Avalon-ST interface.
|DESC_INVALID ||1||Indicates if current descriptor content is valid or stale|
Descriptor contains the source address, destination address and length.
Link = 1
Descriptor contains the address of the next 4 KB page in host memory containing the descriptors.
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