Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 4/20/2022
Public

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8.3.3.3. Completions Management

Kernel module supports two modes of descriptor process completion indication . This is in accordance with the support of the hardware.

  • For both of these modes eventfds are used to pass the completed request counter to the application from the driver
  • The eventfds are passed from the user application to kernel driver using a control message
  • A control message: It is a structure that contains the details of the eventfds, file size (#descriptors per file) and payload size per queue
    • It is passed by the user application before starting of transfer using the read/write system call
    • In order to differentiate between control message & a DMA request, the size must be set to zero in the read/write system call argument to indicate the former
  • The application uses a read operation on the eventfd to acquire the count of completed requests.
Figure 45. Completion Management Flow
In both modes:
  • Updation of the context of the associated descriptor queue also increases the 64 bit counter of the eventfd of the application associated with the queue
  • The application uses read operation on the eventfd to receive the recent number of completed requests
In Interrupt Mode:
  • Upon completion of request the MCDMA IP generates MSI-X signals
  • This interrupt signal invokes the interrupt handler of the driver
  • In the above diagram, steps 1 and 2 of interrupt mode occur asynchronously
In Poll Mode:
  • Application uses poll file operation to poll a channel
  • ifc_device_poll function of kernel driver polls both the queues of the channel and returns flags POLLIN,POLLOUT and/or POLLRDNORM, POLLWRNORM depending on the status of the queues

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