Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 4/20/2022

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Document Table of Contents

5.2. Example Designs

Table 65.  Example Designs




Currently Selected Example Design

PIO using MQDMA Bypass mode (default)

(For AVMM Interface type only) AVMM DMA

Select an example design available from the pulldown list. Avalon-ST/Avalon-MM Interface type setting determines available example designs

Simulation On/Off When On, the generated output includes a simulation model.
Select simulation Root Complex BFM Third-party BFM Intel FPGA BFM

Choose the appropriate BFM for simulation.

Intel FPGA BFM: Default. This bus functional model (BFM) supports x16 configurations by downtraining to x8.

Third-party BFM: Select this If you want to simulate all 16 lanes using a third-party BFM.

Synthesis On/Off When On, the generated output includes a synthesis model.
Generated HDL format


Only Verilog HDL is available in the current release.

Target Development Kit


Intel® Stratix® 10 GX H-Tile Production FPGA Development Kit

Intel® Stratix® 10 MX H-Tile Production FPGA Development Kit

Select the appropriate development board.

If you select one of the development boards, system generation overwrites the device you selected with the device on that development board.
Note: If you select None, system generation does not make any pin assignments. You must make the assignments in the .qsf file.
Note: For more information about example designs, refer to the PCIe Multi-Channel Direct Memory Access IP for H-Tile Design Example User Guide.