Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 4/20/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

7.2. Simulating the IP Core

The Intel® Quartus® Prime Pro Edition software optionally generates a functional simulation model, a testbench or design example, and vendor-specific simulator setup scripts when you generate your parameterized Multi Channel DMA for PCI Express IP core. For Endpoints, the generation creates a Root Port BFM. There is no support for Root Ports in this release of the Intel® Quartus® Prime Pro Edition.

To enable IP simulation model generation, set Create simulation model to Verilog or VHDL when you generate HDL:
Figure 31. Multi Channel DMA IP for PCI Express Simulation in Intel® Quartus® Prime Pro Edition

For information about supported simulators, refer to the Multi Channel DMA for PCI Express Intel FPGA IP Design Example User Guide.

Note: Root Port simulation is supported by VCS only.
Note: The Intel testbench and Root Port BFM provide a simple method to do basic testing of the Application Layer logic that interfaces to the PCIe IP variation. This BFM allows you to create and run simple task stimuli with configurable parameters to exercise basic functionality of the example design. The testbench and Root Port BFM are not intended to be a substitute for a full verification environment. Corner cases and certain traffic profile stimuli are not covered. To ensure the best verification coverage possible, Intel strongly recommends that you obtain commercially available PCIe verification IP and tools, or do your own extensive hardware testing, or both.

Did you find the information on this page useful?

Characters remaining:

Feedback Message