Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 4/20/2022
Public

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3.1.3.2. MSI-X/Writeback

MSI-X and Writeback block update the host with the current processed queue’s head pointer and interrupt. Apart from a global MSI-X Enable and Writeback Enable, there is a provision to selectively enable or disable the MSI-X and Writeback on a per-descriptor basis. This feature can be used by applications to throttle the MSI-X/Writeback.

The table below shows the relation between global and per-descriptor MSI-X/Writeback Enable.
Table 18.  Multi Channel DMA Per-descriptor Enable vs. Global MSI-X/Writeback Enable
Global Enable Per-descriptor Enable MSI-X/Writeback Generation
1 1 On
1 0 Off
0 1 Off
0 0 Off

If enabled, a Writeback is sent to the host to update the status (completed descriptor ID) stored in Q_CONSUMED_HEAD_ADDR location. In addition, for D2H streaming DMA, an additional MWr TLP is issued to the D2H descriptor itself when the IP’s Avalon-ST sink interface has received an sof/eof from the user logic. It updates the D2H descriptor packet information fields such as start of a file/packet(SOF), end of a file/packet(EOF), and received payload count (RX_PYLD_CNT).

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