Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 4/20/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.1.2. D2H Data Mover

The D2H Data Mover (D2HDM) transfers data from device memory to host memory. It receives the data from the user logic through the Avalon-MM Read Master / Avalon-ST Sink interface and generates Mem Wr TLPs to move the data to the host based on descriptor information such as PCIe address (destination), data size, and MPS value to transmit data to the receive buffer in host memory.

In AVMM mode, the D2HDM sends a series of AVMM reads via the master port based on PCIe address, MPS, and DMA transfer size. The AVMM read is generated as follows:
  • First AVMM read to 64-byte address boundary. Multiple bursts are read on first AVMM read if:
    • AVMM address is 64-byte aligned
    • Total payload count of the descriptor is 64-byte aligned and less than max supported MPS
  • Following with AVMM reads with max supported MPS size
  • Last AVMM Read of the remaining size
In AVST mode, D2HDM AVST sink de-asserts ready when descriptors are not available.
  • Host sets up software descriptors for a port. Max payload count can be up to 1MB. SOF/EOF fields in the descriptor may not be set by the Host.
    • D2HDM uses descriptor update sequence to update SOF, EOF, Rx payload count fields in the software descriptor at Host location through a Memory Write request
  • AVST d2h_st_sof_i signal assertion triggers a descriptor update sequence by D2HDM to mark start of AVST frame.
    • D2HDM issues a MWr to set the SOF field in the descriptor
    • WB/MSI-X, if set in the descriptor, is issued
  • AVST d2h_st_eof_i signal assertion triggers a descriptor update sequence by D2HDM to mark end of AVST frame. The descriptor update sequence is as follows:
    • D2HDM terminates the descriptor at d2h_st_eof_i and initiates a descriptor update sequence.
    • During descriptor update sequence, a MWr is issued to set EOF field in the descriptor and update Rx payload count field with total bytes transferred.
    • WB/MSI-X if set in descriptor, is issued
  • The descriptor immediately after EOF sequence, is considered as start of next AVST data frame and initiates a descriptor update sequence to set SOF field.
Note: Descriptor update sequence is performed on SOF/EOF events regardless of global WB/MSI-X being enabled.
When a descriptor is completed, that is, all DMA data corresponding to the descriptor has been sent to the host, the D2HDM performs housekeeping tasks that include:
  • Schedule MSI-X for a completed queue, if enabled in the descriptor
  • Schedule Writeback Consumed Head Pointer for a completed queue, if enabled in the descriptor
  • Update Consume Head Pointer for software polling
  • MSI-X and Writeback are memory write to host via the D2HDM to avoid race condition due to out-of-order writes.

Based on the updated status, software can proceed with releasing the receive buffer and reuse the descriptor ring entries.