Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 4/20/2022
Public

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Document Table of Contents

4.13.1. H2D Data Mover Interface

Table 48.  H2D Data Mover Descriptor Completion Interface (h2ddm_desc_cmpl) Signals
Signal Name I/O Description
h2ddm_desc_cmpl_ready_i Input

Indicates external descriptor controller is ready to accept data.

h2ddm_desc_cmpl_valid_o Output

Qualifies all output signals

x16: h2ddm_desc_cmpl_data_o[511:0]

x8: h2ddm_desc_cmpl_data_o[255:0]

Output

H2D Data Mover descriptor completion data

x16: h2ddm_desc_cmpl_empty_o[5:0]

x8: h2ddm_desc_cmpl_empty_o[4:0]

Output

Specifies number of bytes that are empty during the cycle when h2ddm_desc_cmpl_eop_o is asserted.

These signals are not valid when the h2ddm_desc_cmpl_eop_o is not asserted.

h2ddm_desc_cmpl_sop_o Output

Signals the first cycle of data transfer when used in conjunction with h2ddm_desc_cmpl_valid_o.

h2ddm_desc_cmpl_eop_o Output

Signals the last cycle of data transfer when used in conjunction with h2ddm_desc_cmpl_valid_o.

Table 49.  H2D Data Mover Descriptor Status Interface (h2ddm_desc_status) Signals
Signal Name I/O Description
h2ddm_desc_ready_o Output

Indicates MCDMA IP Core is ready to accept H2D Data Mover descriptor data

h2ddm_desc_valid_i Input

Qualifies H2D Data Mover descriptor data signals

h2ddm_desc_data_i[255:0] Input

H2D Data Mover descriptor data

Table 50.  H2D Data Mover Descriptor Status Interface (h2ddm_desc_status) Signals
Signal Name I/O Description
h2ddm_desc_status_valid_o Output

Qualifies H2D Data Mover descriptor status

h2ddm_desc_status_data_o[31:0] Output

H2D Data Mover descriptor status data

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