Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 4/20/2022

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4.4.2. Avalon-MM Write Master (H2D)

The H2D Avalon-MM Write Master interface is used to write H2D DMA data to the external Avalon-MM slave. This port is 256-bit (x8) / 512-bit (x16) write master that is capable of writing maximum 512 bytes of data per AVMM transaction. The WaitRequestAllowance of this port is enabled and set to 16 allowing the master to transfer continuously 16 data phases after the WaitRequest signal has been asserted.

Table 35.  Avalon-MM Write Master (H2D)

Interface Clock Domain for H-Tile: coreclkout_hip

Interface Clock Domain for P-Tile and F-Tile: app_clk

Signal Name I/O Type Description
h2ddm_waitrequest_i Input H2D Wait Request
h2ddm_write_o Output H2D Write
h2ddm_address_o[63:0] Output H2D Write Address

x16: h2ddm_burstcount_o[3:0]

x8: h2ddm_burstcount_o[4:0]

Output H2D Write Burst Count

x16: h2ddm_writedata_o[511:0]

x8: h2ddm_writedata_o[255:0]

Output H2D Write Data Payload

x16: h2ddm_byteenable_o[63:0]

x8: h2ddm_byteenable_o[31:0]

Output H2D Byte Enable