Multi Channel DMA Intel® FPGA IP for PCI Express User Guide
ID
683821
Date
4/20/2022
Public
A newer version of this document is available. Customers should click here to go to the newest version.
1. Before You Begin
2. Introduction
3. Functional Description
4. Interface Overview
5. Parameters (H-Tile)
6. Parameters (P-Tile and F-Tile)
7. Designing with the IP Core
8. Software Programming Model
9. Registers
10. Troubleshooting/Debugging
11. Multi Channel DMA Intel FPGA IP for PCI Express User Guide Archives
12. Revision History for Multi Channel DMA Intel FPGA IP for PCI Express User Guide
4.1. Port List
4.2. Clocks
4.3. Resets
4.4. Multi Channel DMA
4.5. Bursting Avalon-MM Master (BAM) Interface
4.6. Bursting Avalon-MM Slave (BAS) Interface
4.7. Config Slave Interface (RP only)
4.8. Hard IP Reconfiguration Interface
4.9. Config TL Interface
4.10. Configuration Intercept Interface (EP Only)
4.11. User Functional Level Reset (FLR)
4.12. User Event MSI-X Request Interface
4.13. Data Mover Interface
4.14. Hard IP Status Interface
8.1.6.1. ifc_api_start
8.1.6.2. ifc_mcdma_port_by_name
8.1.6.3. ifc_qdma_device_get
8.1.6.4. ifc_num_channels_get
8.1.6.5. ifc_qdma_channel_get
8.1.6.6. ifc_qdma_acquire_channels
8.1.6.7. ifc_qdma_release_all_channels
8.1.6.8. ifc_qdma_device_put
8.1.6.9. ifc_qdma_channel_put
8.1.6.10. ifc_qdma_completion_poll
8.1.6.11. ifc_qdma_request_start
8.1.6.12. ifc_qdma_request_prepare
8.1.6.13. ifc_qdma_descq_queue_batch_load
8.1.6.14. ifc_qdma_request_submit
8.1.6.15. ifc_qdma_pio_read32
8.1.6.16. ifc_qdma_pio_write32
8.1.6.17. ifc_qdma_pio_read64
8.1.6.18. ifc_qdma_pio_write64
8.1.6.19. ifc_qdma_pio_read128
8.1.6.20. ifc_qdma_pio_write128
8.1.6.21. ifc_qdma_pio_read256
8.1.6.22. ifc_qdma_pio_write256
8.1.6.23. ifc_request_malloc
8.1.6.24. ifc_request_free
8.1.6.25. ifc_app_stop
8.1.6.26. ifc_qdma_poll_init
8.1.6.27. ifc_qdma_poll_add
8.1.6.28. ifc_qdma_poll_wait
8.1.6.29. ifc_mcdma_port_by_name
4.4.1. Avalon-MM PIO Master
The Avalon-MM PIO Master interface is used to write to /read from external registers implemented in the user logic.
Signal Name | I/O Type | Description |
---|---|---|
rx_pio_address_o[n:0] | Output | PIO Read/Write Address. For PIO interface address mapping, refer to Avalon-MM PIO Master |
rx_pio_writedata_o[63:0] | Output | PIO Write Data Payload. |
rx_pio_byteenable_o[7:0] | Output | PIO Write Data Byte Enable. |
rx_pio_write_o | Output | PIO Write. |
rx_pio_read_o | Output | PIO Read |
rx_pio_burstcount_o[3:0] | Output | PIO Write Burst Count. |
rx_pio_waitrequest_i | Input | PIO Write WaitRequest. |
rx_pio_writeresponsevalid_i | Input | PIO response valid to a write request |
rx_pio_readdata_i[63:0] | Input | PIO Read Data. |
rx_pio_readdatavalid_i | Input | PIO Read data valid |
rx_pio_response_i[1:0] | Input | PIO response. Reserved for future release. Tie to 0. |