Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 4/20/2022

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Document Table of Contents

1.2. Known Issues

The following summarizes known issues in the current IP release:
  1. Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.1 and earlier, the User MSI-X feature in the Multi Channel DMA Intel FPGA IP for PCI Express is not functional.
  2. Internal MSI-X / Writeback may be dropped and not sent to the Host due to internal FIFO overflow
  3. Q_COMPLETED_POINTER register (8’h1C) may return incorrect value due to internal FIFO overflow
  4. MCDMA AVMM PIO may drop Posted Writes when user logic backpressures by asserting rx_pio_waitrequest_i
  5. MCDMA BAM mode performance is degraded due to two idle cycles between every transaction
  6. MCMDA BAM module may send malformed TLPs to the integrated Hard IP, causing the Hard IP to generate corrupted packets and LCRC violation
  7. MCDMA example design targeting Intel Stratix 10 DX P-Tile ES1 FPGA Development Kit fails in Intel® Quartus® Prime compilation due to the device OPN (1SD280PT2F55E2VGS1) not supported in Intel® Quartus® Prime software 22.1
  8. In Intel Agilex Gen4 x16 AVST 1 port mode, MCDMA Packet Generate/Check example design in Intel® Quartus® Prime 22.1 may violate setup time requirement at 500 MHz PLD clock frequency.
  9. When software resets a queue by writing 1 to Q_RESET register, other channels stop receiving traffic. You should ensure the system is quiescent before resetting a queue.
  10. In Multi Channel D2H Avalon Streaming, if the channel descriptors are not available or channel's buffer is full, it stalls other channel's data movement until the blocking conditions are removed