Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 4/20/2022
Public

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6.2.2. PCIe0 Configuration, Debug and Extension Options

Figure 21. Endpoint PCIe0 Configuration, Debug and Extension Options
Figure 22. Rootport PCIe0 Configuration, Debug and Extension Options
Table 69.  PCIe0 Configuration, Debug and Extension Options
Parameter Value Default Value Description

Gen 3 Requested equalization far-end TX preset vector

0 - 65535

0x00000004 (for P-Tile)

0x00000200 (for F-Tile)

Specifies the Gen 3 requested phase 2/3 far-end TX preset vector. Choosing a value different from the default is not recommended for most designs.

Gen 4 Requested equalization far-end TX preset vector

0 - 65535

0x00000270 (for P-Tile)

0x00000080 (for F-Tile)

Specifies the Gen 4 requested phase 2/3 far-end TX preset vector. Choosing a value different from the default is not recommended for most designs.

Predetermined number of lanes (for F-Tile)

16

8

4

2

1

Maximum link width

Defines the number of lanes which are connected and good.

Enable HIP Reconfig interface

On / Off

Off

Enables HIP reconfiguration interface

Note: This interface is automatically enabled in Root Port mode. Hence, the parameter is not available for user modification in Root Port mode.

Enable Prefetchable Memory 64-bit address support (Root Port mode only)

On / Off

Off

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