Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 4/20/2022
Public

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6.2.4.1. PCIe0 Device

Table 72.  PCIe0 Device
Parameter Value Default Value Description

Maximum payload size supported

512 Bytes

256 Bytes

128 Bytes

512 Bytes

Specifies the maximum payload size supported. This parameter sets the read-only value of the max payload size supported field of the Device Capabilities registers.

Support Extended Tag Field

On / Off

On

Sets the Extended Tag Field Supported bit in Configuration Space Device Capabilities Register

Note: This parameter is not user configurable. It is set to On by the IP.

Enable multiple physical functions

On / Off

Off

Enables multiple physical functions.

Total virtual functions of physical function 0 (PF0 VFs) 0 - 2048 0

Sets the number of VFs to be assigned to physical function x. This parameter only appears when Enable SR-IOV support is set to On.

By default, only the parameter for physical function 0 appears. If you change the value of Total physical functions (PFs), other parameters appear corresponding to the number of physical functions enabled.

For example, if you set Total physical functions (PFs) to 2, Total virtual functions of physical function 0 (PF0 VFs) and Total virtual functions of physical function 1 (PF1 VFs) appear, allowing you to set the number of virtual functions for each of those physical functions.

Total physical functions (PFs) 1-8 1

Sets the number of physical functions. This parameter only appears when Enable Multiple Physical Functions is set to True.

Enable SR-IOV support On / Off Off

Enable SR-IOV support

Number of DMA channels allocated to PF0 0-512 4

Set the number of DMA channels allocated to the physical function

Number of DMA channels allocated to each VF in PF0 0-512 0

Set the number of DMA channels allocated to each virtual function in the physical function

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