Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 4/20/2022

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Document Table of Contents Avalon-ST 4-Port mode

When you select 4-Port mode, the IP provides 4 Avalon-ST Source ports for H2D DMA and 4 Avalon-ST Sink ports for D2H DMA and supports up to 4 DMA channels. Each port and DMA channel have 1:1 mapping.

Head-of-Line Blocking Prevention

In the mode, if one of the four channels stalls on the user-logic side then a Head-of-the-Line blocking situation could occur since the data movers service each channel in a round-robin arbitration scheme. The H2D and D2H Data Movers service each channel independently based on a round robin arbitration scheme. To prevent Head of Line blocking (HOL) in one of the 4 ports from impacting the performance of other ports, the Multi Channel DMA IP for PCI Express provides up to eight parallel Host-to-device descriptor fetch streams (4 for H2D descriptor fetch & 4 for D2H) and up to four parallel Host-to-device data streams. These data/descriptor fetch streams are independent of each other. Any persisting backpressure from an Avalon-ST Source port might stall one of the four H2D streams. However, the concurrent architecture along with round robin arbitration allows other streams to be mutually exclusive and operate effectively without any impact.

The following is the Avalon-ST interface timing for both H2D and D2H directions. A data transfer happens when both valid and ready signals become ‘1’. Both valid and ready signals can go to ‘0’ within a packet boundary.

Figure 7. Avalon-ST Interface Timing Diagram