Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 4/20/2022
Public

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9.2. MSI-X Memory Space

The MSI-X Table and PBA memory is mapped to the second MB space of the Register address space. Allocated memory space can support up to 2048 MSI-X interrupts for a function. Actual amount of memory depends on the Multi Channel DMA IP for PCI Express configuration.

MSI-X Table

Each entry (vector) is 16 bytes (4 DWORDs) and is divided into Message Address, Data, and Mask (Vector Control) fields as shown in the figure below. To support 2048 interrupts, MSI-X Table requires 32 KB of space per function. But it is mapped to a 512 KB of space.

Figure 52. MSI-X Table Structure

MSI-X PBA

MSI-X PBA (Pending Bit Array) memory space is mapped to a 512 KB region. Actual amount of memory depends on the IP configuration. The Pending Bit Array contains the Pending bits, one per MSI-X Table entry, in array of QWORDs (64 bits). The PBA format is shown below.

Figure 53. MSI-X PBA Structure
Each DMA Channel is allocated 4 MSI-X vectors:
  • 2’b00: H2D DMA Vector
  • 2’b01: H2D Event Interrupt
  • 2’b10: D2H DMA Vector
  • 2’b11: D2H Event Interrupt

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