Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 4/20/2022
Public

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3.1.4. Avalon-MM PIO Master

The Avalon-MM PIO Master bypasses the DMA block and provides a way for the Host to do MMIO read/write to CSR registers of user logic. PCIe BAR2 is mapped to the Avalon-MM PIO Master. Any TLP targeting BAR2 is forwarded to the user logic. TLP address targeting the PIO interface should be 8 bytes aligned. The PIO interface supports non-bursting 64-bit write and read transfers.

The Avalon-MM PIO Master is present only if you select Multi Channel DMA User Mode for MCDMA Settings in the IP Parameter Editor GUI. The Avalon-MM PIO Master is always present irrespective of the Interface type (Avalon-ST/Avalon-MM) that you select.

The PIO interface address mapping is as follows: PIO address = {vf_active, pf [PF_NUM_W-1:0], vf [VF_NUM_W-1:0], address}

  1. vf_active: This indicates that SRIOV is enabled
  2. pf [PF_NUM_W-1:0]: Physical function number decoded from the PCIe header received from the HIP; PF_NUM_W which is ($clog2(Number of PFs)) is the RTL design parameter selected by you such that Multi Channel DMA IP only allocates required number of the bits on Avalon-MM side to limit the number of the wires on the user interface.
  3. vf [VF_NUM_W-1:0]: Virtual function number decoded from the PCIe header received from the HIP; VF_NUM_W which is ($clog2(Number of VFs)) is the RTL design parameter selected by you such that Multi Channel DMA IP only allocates required number of the bits on Avalon-MM side to limit the number of the wires on the user interface.
  4. address: Number of bits required for BAR2 size requested across all Functions (PFs and VFs) Example: If BAR2 is selected as 4 MB, the address size is 22 bits.

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