Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 4/20/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3. Functional Description

Figure 2. Multi Channel DMA IP for PCI Express Block Diagram

Not all the blocks co-exist in a design. Required functional blocks are enabled based on the user mode that you select when you configure the IP. The following table shows valid user modes that Multi Channel DMA IP for PCI Express supports. Each row indicates a user mode with required block(s).

Table 15.  Valid user modes and required functional blocks
Mode MCDMA Bursting Master (BAM) Bursting Slave (BAS) Config Slave (CS) Data Mover
Endpoint MCDMA  
Data Mover Only      
Root Port BAM  

Did you find the information on this page useful?

Characters remaining:

Feedback Message