Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 4/20/2022
Public

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4.4.5. Avalon-ST Sink (D2H)

The D2H Avalon-ST Sink interface is used to read D2H DMA data from the external Avalon-ST source logic.

Table 38.  Avalon-ST Sink (D2H)<n>= 0-3 (4 ports mode) / 0 (1 port mode)
Signal Name I/O Type Description
d2h_st_valid_<n>_i Input Valid for all incoming signals. A ‘1’ represents the device readiness for data to be sent.

x16: d2h_st_data_<n>_i[511:0]

x8: d2h_st_data_<n>_i[255:0]

Input D2H Streaming data from device to host.
d2h_st_ready_<n>_o Output Backpressure from Multi Channel DMA IP for PCI Express. A ‘1’ represents, IP readiness for receiving data.

x16: d2h_st_empty_<n>_i[5:0]

x8: d2h_st_empty_<n>_i[2:0]

Input Represents the number of empty bytes in d2h_st_data_<n>_i, and valid only when both d2h_st_valid__<n>_i and d2h_st_eop__<n>_i is ‘1’.
d2h_st_sof_<n>_i Input Start of file (or packet) as instructed by the user logic.
d2h_st_eof_<n>_i Input End of file (or packet) as instructed by the user logic.
d2h_st_channel_<n>_i[10:0] input To support multi-Channel per port.

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