ALTPLL (Phase-Locked Loop) IP Core User Guide

ID 683732
Date 6/16/2017
Document Table of Contents

ALTPLL (Phase-Locked Loop) IP Core User Guide

Updated for:
Intel® Quartus® Prime Design Suite 17.0
The Altera Phase-Locked Loop (ALTPLL) IP core implements phase lock loop (PLL) circuitry. A PLL is a feedback control system that automatically adjusts the phase of a locally generated signal to match the phase of an input signal. PLLs operate by producing an oscillator frequency to match the frequency of an input signal. In this locked condition, any slight change in the input signal first appears as a change in phase between the input signal and the oscillator frequency.

This phase shift then acts as an error signal to change the frequency of the local PLL oscillator to match the input signal. The locking-onto-a-phase relationship between the input signal and the local oscillator accounts for the name phase-locked loop. PLLs are often used in high-speed communication applications

You can use the Quartus® Prime IP Catalog and parameter editor to specify PLL parameters .

Note: This IP core does not support Arria® 10 designs.