ALTPLL (Phase-Locked Loop) IP Core User Guide
|Intel® Quartus® Prime Design Suite 17.0|
This phase shift then acts as an error signal to change the frequency of the local PLL oscillator to match the input signal. The locking-onto-a-phase relationship between the input signal and the local oscillator accounts for the name phase-locked loop. PLLs are often used in high-speed communication applications
You can use the Quartus® Prime IP Catalog and parameter editor to specify PLL parameters .
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